1. Field of Invention
The invention is directed to a process for hardening a photoresist applied to the surface of a semiconductor wafer during chip fabrication.
2. Description of the Prior Art
Semi-conductor chips are manufactured in a multi-step process. Initially, during the wafer preparation step, semiconductor crystals are sliced into thin sheets which are polished to free them of surface irregularities. Thereafter, the prepared wafers undergo fabrication in which devices such as integrated circuits or chips are imprinted. Each chip carries multiple thin layers of conducting metals, semiconductors and insulating materials. Layering may be accomplished by growing or by deposition. After a layer is applied, it is further processed in a series of patterning steps, in which portions of the added layer are removed. Doping and heat treatment steps also are necessary during chip fabrication. A plurality of layers are applied, patterned, doped and heat treated during fabrication to create the finished chip.
Photolithography is a multi-step process and is one of the basic techniques used in patterning. With reference to FIG. 1a, conventional semiconductor substrate 1 includes layer 2 disposed thereon in a conventional manner. The object of photolithography is to pattern layer 2 and thus layer 2 generally is referred to as the patterned layer. Patterned layer 2 may be made of a metal, oxide or semiconductor material, and is patterned during photolithography by selectively removing material at specified locations. Photoresist layer 3 is applied to the surface of patterned layer 2 in a conventional manner and is made of a conventional light sensitive material which changes properties when exposed to light. For example, photoresist layer 3 may be a polyvinylphenol (PVP). Photoresist layer 3 is selectively exposed to light such as X-ray or ultraviolet light by making use of mask 4 which blocks transmission of light to photoresist layer 3 at selective locations. The pattern of mask 4 matches the pattern which ultimately is to be formed in patterned layer 2.
The properties of the exposed surface area of photoresist layer 3 are changed by the exposure. For example, the exposed surface area may be made it insoluble to certain chemical solvents which are used as developers. Accordingly, by applying developer to exposed photoresist layer 3, the surface area thereof which has been exposed to the light and made insoluble is removed by the developer to leave holes in photoresist layer 3 which correspond to the unblocked region in mask 4. As shown in FIG. 1b, the holes isolate a plurality of islands 3a which correspond to mask 4. In other words, the pattern of mask 4 is transferred to photoresist layer 3 during development.
The pattern of photoresist layer 3 which now has the form of islands 3a is transferred to patterned layer 2 by a conventional etching process, for example, by wet etching in which the substrate is immersed in a tank of chemical etchant. Photoresist layers are etch resistant, that is, they do not dissolve in chemical etching solutions. Accordingly, the areas of patterned layer 2 which are covered by polymerized photoresist islands 3a are not dissolved in the etching solution thereby forming features 2a. The areas which are not covered are removed by the etching to create openings or trenches between features 2a, thereby completing transfer of the desired pattern to patterned layer 2. Thereafter, islands 3a are removed by a conventional process, for example, by wet chemical or plasma stripping which does not affect either patterned layer 2 or substrate 1. As a result, as shown in FIG. 1d, substrate layer 1 is formed to have a desired patterned layer 2 thereon. A conventional photolithograpy process is described in U.S. Pat. No. 5,001,039 to Ogoh, incorporated by reference.
At various times during the photolithography process, substrate 1 having layers 2 and 3 thereon is subjected to high temperatures. For example, the developed substrate (FIG. 1b) is subjected to high temperatures during etching, for example, temperatures up to about 150.degree. C. The high temperatures cause thermal flow and rapid volume reduction of the photoresist material, and a resultant profile degradation. For example, developed photoresist layer 3 having both small features 3a and a large feature 3b is shown in FIG. 2a. Both the large and small features have relatively regular, well-defined shapes, that is, they have relatively straight upper and side surfaces. However, due to thermal flow and volume reduction, the large and small features assume the irregular shapes shown in FIG. 2b in which the upper surfaces become relatively rounded. The larger photoresist features undergo more volume reduction than the smaller photoresist features and thus, in general, the larger features undergo greater profile degradation than the smaller features at the edges of the photoresist pattern.
The problems which result from the profile degradation illustrated in FIGS. 2a-b are shown in FIGS. 3a-c. FIGS. 3a and 3b are overhead and cross-sectional views, respectively, of a portion of substrate 1 having patterned layer 2 and developed photoresist layer 3 thereon. In this instance, the development of photoresist layer 3 has created relatively large features defining an island 3c devoid of the resist material. The results of the etching process are shown in FIG. 3c. Due to the large profile degradation of large features 3b of photoresist layer 3 which resulted in the formation of an irregular surface during etching, irregularly shaped features are formed in patterned layer 2. The irregular features define opening or trench 10 which has an irregular shape. In particular, trench 10 is formed with tapered instead of vertical side walls, giving the trench an overall V-shape with a widened bottom. The width of the features of patterned layer 2 is critical to the formation of circuits which function in accordance with the desired design criteria. Accordingly, a finished patterned layer 2 including irregularly shaped trench 10 having a width which varies from top to bottom could result in a defective circuit.
A similar situation is shown in FIGS. 4-c. In this situation developed photoresist layer 3 includes a plurality of relatively small features 3a defining a plurality of islands therebetween which are void of resist material. As shown in FIG. 4c, though the etching process causes profile degradation of small features 3a, the degradation is less than that of large features 3b as in FIG. 3c. Thus, after etching the features of patterned layer 2 are less irregular than the features of patterned layer 2 in FIG. 3c. In some instances, the effect of profile degradation on the final shape of the features of the patterned layer may be minimal enough so that after etching the features of the patterned layer are still within desired design parameters. Of course, whether the degree of profile degradation and the resultant effect upon the features of the patterned layer is acceptable ultimately depends upon the critical dimensions tolerance of the chip and the etching performance.
In order to overcome the drawbacks resulting from profile degradation, it is necessary to harden the developed photoresist layer before proceeding with the etching process. One manner of hardening known in the prior art is hard baking, in which the substrate having patterned layer 2 and photoresist layer 3 thereon is baked in an oven, for example, at 130.degree. C. for approximately two minutes. The baking drives water and solvents out of the photoresist and further polymerizes photoresist layer 3 to make it more etch resistant. However, the upper limit of the hard bake is set by the thermal flow point of the resist. If this limit is exceeded, profile degradation occurs even before etching. Accordingly, hard baking is insufficient to resist the degradation experienced during the etching itself.
Another prior art technique for hardening includes heating the developed photoresist layer with simultaneous exposure to Ultraviolet (UV) radiation. This technique can be performed with a conventional UV lamp with the substrate disposed on a conventional hot plate. A device for performing this function is disclosed in U.S. Pat. No. 4,900,938 to Suzuki et at, incorporated by reference. With reference to FIG. 5, device 20 includes support 22 disposed in isolated chamber 24. Support 22 includes heater 26 disposed therein, which includes cooling conduits 28 and lead wire 30 for connecting to a power source. UV radiation provided by lamp 32 reflects off of mirror 34 and is projected through window 36 and shutter 38. Device 20 also includes an intake 40 and exhaust hole 42 which allow for evacuation of atmospheric gases and filling of the chamber with inert gases. In order to effectively harden the resist without creating thermal flow, the UV radiation should be at a wavelength of 200-400 nm, and the temperature should be at least 0.degree. C. and not exceed 90.degree. C. However, this prior art method of hardening causes pattern shrinkage of the features of photoresist layer 3. For example, the line width of the resist features may be decreased by 10%.
During chip fabrication, it is desired to form features in patterned layer 2 having the smallest possible spacing. In some cases it is desired to form patterned layer features which have spacings therebetween of as little as 0.25 .mu.m. The pattern shrinkage discussed above makes it difficult to achieve spacings which are this small. FIG. 6a shows in representative cross section a plurality of resist features 3a having a line width 1 and spacing s both before (upper view) and after (lower view) treatment by the above-discussed hardening process combining UV irradiation and heat. As shown, before treatment line width l is approximately equal to spacing s, for example, both 1 and s may be approximately equal to 0.25 .mu.m. However, after treatment, due to pattern shrinkage, the line widths l decrease, resulting in a corresponding increase in the spacing s between features. For example, the spacing may increase to 0.28 .mu.m. The increase in spacing s will be transferred to the patterned layer and thus, the desired close spacing will not be achieved.
With reference to FIG. 6b, in order to ensure that the features of photoresist layer 3 and thus the features of patterned layer 2 will be spaced sufficiently close to each other, photoresist layer 3 could be developed with features which are spaced extremely close to each other, as shown in the upper view. For example, the features may have line widths 1 approximately equal to 0.28 .mu.m, and may have a spacing of approximately 0.22 .mu.m. Thus, even after the pattern shrinkage and corresponding increase in spacing s caused by the hardening process, the spacing s still will be sufficiently small. For example, after hardening, both the line spacing s and line width 1 may become 0.25 .mu.m, as shown in the lower view. Thus, after etching, the features of patterned later 2 also would be spaced sufficiently close together. However, in practice, it is extremely difficult to achieve spacings of 0.2-0.22 .mu.m in developed photoresist layer 3. Such spacings require the use of photomasks having extremely high resolution, and production of such masks are not practical.
Current photolithography processes may provide developed photoresist layers having spacing s approximately equal to about 0.25 .mu.m. However, as discussed, the shrinkage of the features which results from the known hardening processes results in an unsatisfactory increase in spacing s of the photoresist features, and a corresponding unsatisfactory increase in the spacing of the features in the patterned layer. For example, the line widths may shrink to about 0.22 .mu.m and the spacing may increase to about 0.28 .mu.m. Thus, shrinkage of the photoresist layers during the hardening process results in a limit on how closely the features of the patterned layer can be formed to each other. Alternatively, the shrinkage caused by the known hardening processes may be taking into account by forming the photoresist layer to have features which are spaced extremely close to each other, for example, 0.22 .mu.m. After the pattern shrinkage and corresponding increase in spacing, the features of the photoresist and thus of the patterned layer still would have a satisfactory small spacing. However, in practice, it is not practical to form developed photoresist layers with spacings this small due to the practical limits on the resolution of the photomasks. Accordingly, there is a practical limit to how closely the features of the patterned layer can be spaced from each other in prior art patterning methods.